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Single-chip Type with Built-in FET Switching Regulator Series
Output 1.5A or Less High Efficiency Step-down Switching Regulator with Built-in Power MOSFET
BD9152MUV
No.09027EAT14
Description ROHM's high efficiency dual step-down switching regulator BD9152MUV is a power supply designed to produce a low voltage including 3.3,0.8 volts from 5.5/4.5 volts power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load.
Features 1)Offers fast transient response with current mode PWM control system. 2)Offers highly efficiency for all load range with synchronous rectifier (Pch/Nch FET) and SLLM (Simple Light Load Mode) 3)Incorporates soft-start function. 4)Incorporates thermal protection and ULVO functions. 5)Incorporates short-current protection circuit with time delay function. 6)Incorporates shutdown function Icc=0A(Typ.) 7)Employs small surface mount package : VQFN020V4040
Use Power supply for LSI including DSP, Micro computer and ASIC
Absolute Maximum Rating (Ta=25)
Parameter Vcc Voltage EN Voltage SW Voltage Symbol VCC VEN1 VEN2 VSW1 VSW2 Pd1 Power Dissipation Pd2 Pd3 Pd4 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature
1 2 3 4 5
Limit -0.3+7 * -0.3+7 -0.3+7 -0.3+7 -0.3+7 0.34*
2 3 4 1
Unit V V V V V W W W W
0.70 * 1.21 * 3.56*
5
Topr Tstg Tjmax
-40+85 -55+150 +150
Pd should not be exceeded.
IC only
1-layer. mounted on a 74.2mmx74.2mmx1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 4-layer. mounted on a 74.2mmx74.2mmx1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 , in each layers 4-layer. mounted on a 74.2mmx74.2mmx1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers
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1/17
2009.05 - Rev.A
BD9152MUV
Operating Conditions (Ta=-40+105)
Parameter Vcc Voltage EN Voltage Output Voltage range SW Average Output Current
6
Technical Note
Symbol
Min.
Typ.
Max.
Unit
VCC VEN1 VEN2 VOUT2 ISW1 ISW2
4.5 0 0 0.8 -
5.0 -
5.5 5.5 5.5 2.5 1.5*6 1.5*6
V V V V A A
Pd and ASO should not be exceeded.
Electrical Characteristics BD9152MUV (Ta=25 VCC=5V, EN1=EN2=VCC ,unless otherwise specified.)
Parameter Standby Current Bias Current EN Low Voltage EN High Voltage EN Input Current Oscillation Frequency Pch FET ON Resistance Symbol Min. ISTB ICC VENL VENH IEN FOSC RONP1 RONP2 RONN1 RONN2 FB1 FB2 VUVLOL1 VUVLOH1 VUVLOL2 VUVLOH2 RFB1 TSS TLATCH VSCP1 VSCP2 1.0 2 0.8 3.25 0.788 3.6 3.65 2.4 2.425 0.4 2.0 1.65 0.4 Limit Typ. 0 500 GND Vcc 1 1.0 0.17 0.17 0.13 0.13 3.3 0.8 3.8 3.9 2.5 2.55 20 0.8 4.0 2.4 0.56 Max. 10 800 0.8 10 1.2 0.3 0.3 0.2 0.2 3.35 0.812 4.0 4.2 2.6 2.7 40 1.6 ms V V A A V V A MHz V V V V V V ms SCP/TSD ON FB1=3.30V FB2=0.80V Vcc=5V Vcc=5V Vcc=5V Vcc=5V 1.5% 1.5% Vcc=50V Vcc=05V Vcc=50V Vcc=05V Vcc=5V Standby Mode Active Mode EN1=EN2=2V EN1=EN2=0V Unit Condition
Nch FET ON Resistance
FB Reference Voltage UVLO Threshold Voltage1 UVLO Release Voltage1 UVLO Threshold Voltage2 UVLO Release Voltage2 FB1 Discharge Resistance Soft Start Time Timer Latch Time Output Short circuit Threshold Voltage
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2/17
2009.05 - Rev.A
BD9152MUV
Technical Note
Block Diagram, Application Circuit BD9152MUV
FB1 PVCC
Current Comp EN1 Gm Amp R S Q
4.00.1
4.00.1
D9152
EN1
Lot No.
Current Sense/ Protect + Driver Logic
SW1
Slope1 AGND
Soft Start1
1.0Max.
ITH1
PGND1
SCP1
S
0.02 +0.03 -0.02 (0.22)
CLK1
0.08 S
VREF
OSC
CLK2
SCP/ TSD
UVLO1 UVLO2
C0.2 2.10.1
1 5
SCP2
PVCC
Current
0.40.1
2.10.1
20 16 15 11
6
Current Comp Gm Amp R S Slope2 Q
Sense/ Protect + Driver Logic
10
FB2 EN2 ITH2
Soft Start2
SW2
1.0
0.5
0.25 +0.05 -0.04
(Unit : mm)
CLK2
PGND2
Fig.1 BD9152MUV TOP View
AGND
Fig.2 BD9152MUV Block Diagram
Pin No. & function table Pin Pin No. name 1 2 3 4 5 6 7 8 9 10 PGND2 PVcc PVcc PVcc PGND1 PGND1 SW1 SW1 EN1 FB1
Function
Pin No. 11 12 13 14 15 16 17 18 19 20
Pin name ITH1 AGND N.C. AVcc ITH2 FB2 EN2 SW2 SW2 PGND2
Function Ch1 GmAmp output pin/ Connected phase compensation capacitor Ground Non Connection VCC power supply input pin Ch1 GmAmp output pin/Connected phase compensation capacitor Ch2 output voltage detect pin Ch2 Enable pin(High Active Ch2 Pch/Nch FET drain output pin Ch2 Pch/Nch FET drain output pin Ch2 Lowside source pin
Ch2 Lowside source pin Highside FET source pin Highside FET source pin Highside FET source pin Ch1 Lowside source pin Ch1 Lowside source pin Ch1 Pch/Nch FET drain output pin Ch1 Pch/Nch FET drain output pin Ch1 Enable pin(High Active) Ch1 output voltage detect pin
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3/17
2009.05 - Rev.A
BD9152MUV
Characteristics dataBD9152MUV
3.5 3.0
OUTPUT VOLTAGE:VOUT[V]
Technical Note
3.5
3.5
OUTPUT VOLTAGE:VOUT[V]
2.5 2.0 1.5 1.0 0.5 0.0 0
VOUT1=3.3V VOUT2=1.2V
2.5 2.0
OUTPUT VOLTAGE:VOUT[V]
Ta=25 Io=1.5A
3.0
VOUT1=3.3V
3.0 2.5 2.0 1.5 1.0 0.5 0.0
VOUT1=3.3V
VOUT2=1.2V
1.5 1.0 0.5 0.0
VOUT2=1.2V
VCC=5V Ta=25 Io=0A
0 1 2 3 4 5
VCC=5V Ta=25
0 1 2 3 OUTPUT CURRENT:IOUT [A] 4
1
2 3 4 INPUT VOLTAGE:VCC[V]
5
EN VOLTAGE:VEN[V]
Fig.3 VCC - VOUT1,VOUT2
3.40
1.25
Fig.4 VEN - VOUT
100
Fig.5 IOUT - VOUT
VOUT1=3.3V
OUTPUT VOLTAGE:VOUT[V] OUTPUT VOLTAGE:VOUT[V]
VOUT2=1.2V VOUT2=1.2V
EFFICIENCY:[%]
90 80 70 60 50 40 30 20 10 0
VOUT1=3.3V VOUT2=2.5V
3.35
1.23
VOUT2=1.5V
3.30
1.20
VOUT2=1.2V
3.25
VCC=5V Io=0A
-40 -20 0 20 40 60 TEMPERATURE:Ta[] 80
1.18
VCC=5V Io=0A
-40 -20 0 20 40 60 TEMPERATURE:Ta[] 80
VCC=5V Ta=25
10
3.20
1.15
VOUT2=1.0V 100 1000 OUTPUT CURRENT:IOUT[mA]
10000
Fig. 6 Ta-VOUT1
1.2 1.0 FREQUENCY:FOSC[MHz] 0.8 0.6 0.4 0.2 0.0
-40 -20 0 20 40 60 80
Fig. 7 Ta-VOUT2
200 175
Fig.8 Efficiency
1.1
VCC=5V
PMOS
FREQUENCY:FOSC[MHz]
ON RESISTANCE:RON[m]
1
150 125 100 75 50 25 0
0.9
NMOS
0.8
VCC=5V
Ta=25
0.7 4.5
TEMPERATURE:Ta[]
4.75 5 5.25 INPUT VOLTAGE:VCC[V]
5.5
-40
-20
0 20 40 60 80 TEMPERATURE:Ta[]
100
Fig.9 Ta- Fosc
2.0 1.8 1.6
EN VOLTAGE:VEN[V]
Fig.10 VCC-Fosc
600
Fig.11 Ta - RONN, RONP
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
-40 -20 0 20 40 60 80
CIRCUIT CURRENT:ICC[A]
500 400
VCC=5V,Ta=25
EN1=E2
300 200
VOUT1
VCC=5V
VCC=5V
100 0
-40 -20 0 20 40 60 80
VOUT2
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
Fig.12 TaEN1,EN2
Fig.13 TaIcc
Fig.14 Soft start wave form (Io=0mA)
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4/17
2009.05 - Rev.A
BD9152MUV
Characteristics dataBD9152MUV
Technical Note
VCC=5V,Ta=25
SW1 EN1=E2
VCC=5V,Ta=25
SW1
VCC=5V,Ta=25
VOUT1 VOUT1 VOUT2 VOUT1
Fig.15 Soft start wave form (Io=1.5A)
Fig.16 SW1 wave form (Io=0mA)
Fig.17 SW1 wave form (Io=1.5A)
VCC=5V,Ta=25,VOUT2=1.2V
SW2
VCC=5V,Ta=25,VOUT2=1.2V
VOUT1
VCC=5V,Ta=25
VOUT2
IOUT1
Fig.18 SW2 wave form (Io=0mA)
Fig.19 SW2 wave form (Io=1.5A)
Fig.20 VOUT1 transient responce (Io0.5A1.5A / usec)
VCC=5V,Ta=25
VOUT2
VCC=5V,Ta=25,VOUT2=1.2V
VOUT2
VCC=5V,Ta=25,VOUT2=1.2V
IOUT2
IOUT2
Fig.21 VOUT1 transient responce (Io1.5A0.5A/ usec)
Fig.22 VOUT2 transient responce (Io0.5A1.5A/ usec)
Fig.23 VOUT2 transient responce (Io1.5A0.5A/ usec)
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5/17
2009.05 - Rev.A
BD9152MUV
Information on advantages Advantage 1Offers fast transient response with current mode control system. Conventional product (Load response IO=0.5A1.5A)
Technical Note
BD9152MUV (Load response IO=1.5A0.5A)
VOUT1
VOUT1
IOUT
IOUT
Fig.24 Transient response Advantage 2 Offers high efficiency for all load range. For lighter load: Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load. For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. ON resistance of Highside MOS FET : 170m(Typ.) ON resistance of Lowside MOS FET : 130m(Typ.)
100 Efficiency [%] SLLM 50 PWM
inprovement by SLLM system improvement by synchronous rectifier
Achieves efficiency improvement for heavier load. Offers high efficiency for all load range with the improvements mentioned above.
0 0.001
0.01 0.1 Output current Io[A]
1
Fig.25 Efficiency
Advantage 3Supplied in smaller package due to small-sized power MOS FET incorporated. Output capacitor Co required for current mode control: 22F ceramic capacitor Inductance L required for the operating frequency of 1 MHz: 2.2H inductor Incorporates FET + Boot strap diode Reduces a mounting area required.
L1
FB1 ITH1 EN1 SW1 SW1 PGND1 PGND1 PVcc PVcc PVcc PGND2 EN2 SW2 SW2 PGND2
VOUT1 COUT1
20mm COUT1 CIN1 COUT2
RITH1
AGND N.C. AVcc ITH2
CIN1 CIN2
15mm L1 R1 L2
RITH2
FB2
COUT2
RITH1 RITH2 R2 CITH1 CITH2
VOUT2
L2
R2 R1
Fig.26 Example application
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6/17
2009.05 - Rev.A
BD9152MUV
Technical Note
Operation BD9152MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency. Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a highside MOS FET (while a lowside MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET (while a lowside MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation. SLLM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency.
SENSE Current Comp RESET Level Shift Gm Amp. ITH OSC RQ FB SET S Driver Logic SW Load IL VOUT
VOUT
Fig.27 Diagram of current mode PWM control
PVCC SENSE FB SET GND GND GND IL(AVE) SET PVCC SENSE FB GND GND
Current Comp
Current Comp
RESET SW IL
RESET SW
GND IL 0A
VOUT
VOUT(AVE)
VOUT
VOUT(AVE)
Not switching
Fig.28 PWM switching timing chart
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Fig.29 SLLMTM switching timing chart
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2009.05 - Rev.A
BD9152MUV
Technical Note
Description of operations Soft-start function EN terminal shifted to "High" activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. Shutdown function With EN terminal shifted to "Low", the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0F (Typ.). UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 50mV (Typ.) is provided to prevent output chattering. Each the outputs have UVLO. It is possible to set output sequence easy.
VCC
Hysteresis 100mV
Hysteresis 50mV
EN1,2
VOUT1
TSS discharge ON discharge ON TSS discharge ON TSS discharge ON
VOUT2
TSS
Natural discharge
Natural discharge TSS TSS
Natural discharge
Ch1 Standby mode Ch2 Standby mode Ch1, Ch2 Operating mode Ch1 : standby mode Ch2 : Operating mode
Standby mode Ch1, Ch2 Operating mode
Ch1 Standby mode Ch2 Standby mode
Ch1, Ch2 Standby mode
Ch1, Ch2 Operating mode
UVLO2 UVLO1
UVLO1
UVLO1 UVLO2
EN
EN
UVLO1 UVLO2
Fig.30 Soft start, Shutdown, UVLO timing chart
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8/17
2009.05 - Rev.A
BD9152MUV
Technical Note
Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO.
EN1EN2 Output Short circuit Threshold Voltage VOUT2 Output OFF Latch
IL Limit
IL1
Standby mode
t1t2=TLATCH
Standby mode
Operating mode
EN
Timer latch
EN
Fig.31 Short-current protection circuit with time delay timing chart
Switching regulator efficiency Efficiency may be expressed by the equation shown below: = VOUTxIOUT VinxIin x100[%]= POUT Pin x100[%]= POUT POUT+PD x100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PD as follows: Dissipation factors: 2 1) ON resistance dissipation of inductor and FETPD(I R) 2) Gate charge/discharge dissipationPD(Gate) 3) Switching dissipationPD(SW) 4) ESR dissipation of capacitorPD(ESR) 5) Operating current dissipation of ICPD(IC)
2 2 1)PD(I R)=IOUT x(RCOIL+RON) (RCOIL[]DC resistance of inductor, RON[]ON resistance of FET, IOUT[A]Output current.) 2)PD(Gate)=CgsxfxV (Cgs[F]Gate capacitance of FET, f[H]Switching frequency, V[V]Gate driving voltage of FET) 2 Vin xCRSSxIOUTxf
3)PD(SW)=
IDRIVE
(CRSS[F]Reverse transfer capacitance of FET, IDRIVE[A]Peak current of gate.)
2 4)PD(ESR)=IRMS xESR (IRMS[A]Ripple current of capacitor, ESR[]Equivalent series resistance.) 5)PD(IC)=VinxICC (ICC[A]Circuit current.)
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9/17
2009.05 - Rev.A
BD9152MUV
Technical Note
Consideration on permissible dissipation and heat generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation.
4.5
4 layers (copper foil area : 5505mm ) (copper foil in each layers) j-a=35.1/W 2 4 layers (copper foil area : 10.29mm ) (copper foil in each layers) j-a=103.3/W 2 1 layer (copper foil area : 0mm ) j-a=178.6/W IC only j-a=367.6/W
2
4.0 3.56W
P=IOUT xRON RON=DxRONP+(1-D)RONN DON duty (=VOUT/VCC) RONHON resistance of Highside MOS FET RONLON resistance of Lowside MOS FET IOUTOutput current
2
Power dissipation : Pd [W]
3.0
2.0 1.21W 1.0 0.70W 0.34W 0 0 25 50 75 100 105 125 150
Ambient temperature :Ta []
Fig.32 Thermal derating curve (VQFN020V4040) (Example) VCC=5V, VOUT1=3.3V, VOUT2=1.2V, RONH=170m, RONL=130m IOUT=1.5A, for example, D1=VOUT1/VCC=3.3/5=0.66 D2=VOUT2/VCC=1.2/5=0.24 RON1=0.66x0.170+(1-0.66)x0.130 =0.1122+0.0442 =0.1564[] RON2=0.24x0.170+(1-0.24)x0.130 =0.0408+0.0988 =0.1397[] P=1.52x0.1564+1.52x0.1397=0.666[W] As RONH is greater than RONL in this IC, the dissipation increases as the ON duty becomes greater. consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed. With the
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10/17
2009.05 - Rev.A
BD9152MUV
Selection of components externally connected 1. Selection of inductor (L)
IL IL
Technical Note
VCC
The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. (VCC-VOUT)xVOUT IL= [A](1) LxVCCxf Appropriate ripple current at output should be 20% more or less of the maximum output current. IL=0.2xIOUTmax. [A](2) L= (VCC-VOUT)xVOUT ILxVCCxf [H](3)
IL VOUT L Co
Fig.33 Output ripple current
(IL: Output ripple current, and f: Switching frequency)
Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=5.0V, VOUT=1.2V, f=1.0MHz, IL=0.3x1.5A=0.45A, for example,(BD9152MUV) (5-1.2)x1.2 0.45x5x1.0M
L=
=2.02 2.2[H]
Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency.
2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage.
VOUT
Output ripple voltage is determined by the equation (4) VOUT=ILxESR [V](4) (IL: Output ripple current, ESR: Equivalent series resistance of output capacitor) Rating of the capacitor should be determined allowing sufficient margin against output voltage. A 22F to 100F ceramic capacitor is recommended. Less ESR allows reduction in output ripple voltage.
L
ESR Co
Fig.34 Output capacitor
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11/17
2009.05 - Rev.A
BD9152MUV
Technical Note
3. Selection of input capacitor (Cin)
VCC
Cin
Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. The ripple current IRMS is given by the equation (5):
VOUT
L
Co
IRMS=IOUTx
VOUT(VCC-VOUT)
VCC < Worst case > IRMS(max.) IOUT
[A](5)
Fig.35 Input capacitor
2 If VCC=5.0V, VOUT=1.8V, and IOUTmax.=1.5A, (BD9152MUV) IRMS=2x 1.8(5.0-1.8) 5.0 =0.48[ARMS]
When Vcc=2xVOUT, IRMS=
A low ESR 22F/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.) A Gain [dB] fp(Max.) 0 fz(ESR) IOUTMin. 0 IOUTMax.
fp=
1 2xROxCO 1 fz(ESR)= 2xESRxCO Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. fp(Min.)= 1 [Hz]with lighter load 2xROMax.xCO 1 2xROMin.xCO [Hz] with heavier load
Phase [deg]
-90
Fig.36 Open loop gain characteristics fp(Max.)=
A Gain [dB] 0 0 Phase [deg] -90
fz(Amp.)
Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.) fz(Amp.)= 1 2xRITHxCITH
Fig.37 Error amp phase compensation characteristics
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12/17
2009.05 - Rev.A
BD9152MUV
Technical Note
VOUT1 L1
FB1 ITH1 EN1 SW1 SW1 PGND1 PGND1 PVcc PVcc PVcc PGND2 EN2 SW2 SW2 PGND2
ESR COUT1
RO1
RITH1 CITH1
AGND N.C. AVcc ITH2
CIN1 CIN2
RITH2 CITH2
FB2
COUT2
VOUT2 L2 R2 R1 RO2
Fig.38 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.) 1 2xRITHxCITH = 1 2xROMax.xCO
5. Determination of VOUT2 output voltage The output voltage VOUT2 is determined by the equation (6): VOUT2=(R2/R1+1)xVFB2(6) VFB2: Voltage at ADJ terminal (0.8V Typ.) With R1 and R2 adjusted, the output voltage may be determined as required.
L2 VOUT2 SW2 Cout2 R2
FB2
Adjustable output voltage range : 0.8V2.5V
R1
Fig.39 Determination of output voltage
Use 1 k100 k resistor for R1. If a resistor of the resistance higher than 100 k is used, check the assembled set carefully for ripple voltage etc.
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13/17
2009.05 - Rev.A
BD9152MUV
BD9152MUV Cautions on PC Board layout
VOUT1 COUT1
Technical Note
L1
FB1 EN1 SW1 SW1 PGND1 ITH1
RITH1 CITH1
PGND1 PVcc PVcc PVcc PGND2 EN2 SW2 SW2 PGND2
AGND N.C. AVcc ITH2
CIN1 CIN2
RITH2 CITH2
FB2
COUT2 VOUT2
L2
R2
R1
Fig.40 Layout diagram Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. VQFN020V4040 (BD9152MUV) has thermal PAD on the reverse of the package. The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of PCB.
Recommended components Lists on above application Symbol L1,2 CIN1,CIN2 Cout1,Cout2 CITH1 RITH1 Coil Ceramic capacitor Ceramic capacitor Ceramic capacitor Resistance Part Value 2.2uH 22uF 22uF 680pF 82k VOUT2=0.8V VOUT2=1.0V CITH2 Ceramic capacitor VOUT2=1.2V VOUT2=1.5V VOUT2=1.8V VOUT2=2.5V VOUT2=0.8V VOUT2=1.0V VOUT2=1.2V VOUT2=1.5V VOUT2=1.8V VOUT2=2.5V 680pF 680pF 680pF 680pF 680pF 680pF 12k 12k 15k 15k 33k 82k Manufacturer TDK Murata Murata Murata Rohm Murata Murata Murata Murata Murata Murata Rohm Rohm Rohm Rohm Rohm Rohm Series LTF5022-2R2N3R2 GRM32EB11A226KE20 GRM31CB30J226KE18 GRM18 Series MCR03 Series GRM18 Series GRM18 Series GRM18 Series GRM18 Series GRM18 Series GRM18 Series MCR03 Series MCR03 Series MCR03 Series MCR03 Series MCR03 Series MCR03 Series
RITH2
Resistance
The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins.
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14/17
2009.05 - Rev.A
BD9152MUV
I/O equivalence circuit BD9152MUV
PVCC PVCC PVCC
Technical Note
EN1,EN2 pin
SW1,SW2
EN1,EN2 SW1,SW2
FB1,FB2 pin
ITH1,ITH2 pin
AVCC
FB1,FB2 ITH1,ITH2
Fig.41 I/O equivalence circuit
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15/17
2009.05 - Rev.A
BD9152MUV
Cautions on use
Technical Note
1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 5. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 6. Input to IC terminals + This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 42. P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements. Resistor Pin A Pin A
P+ N P P+ C B E B P P+ N C E
Transistor (NPN) Pin B
N
N
Parasitic element
N
P+
N
P substrate Parasitic element
GND
P substrate Parasitic element
GND GND GND
Parasitic element
Other adjacent elements
Fig.42 Simplified structure of monorisic IC 7. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
8 . Selection of inductor It is recommended to use an inductor with a series resistance element (DCR) 0.15 or less. Note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF. When using an inductor over 0.15, be careful to ensure adequate margins for variation between external devices and this IC, including transient as well as static characteristics.
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16/17
2009.05 - Rev.A
BD9152MUV
Ordering part number
Technical Note
B
D
9
Part No.
1
5
2
M
U
V
-
E
2
Part No.
Package MUV: VQFN020V4040
Packaging and forming specification E2: Embossed tape and reel
VQFN020V4040
4.00.1
4.00.1

Tape Quantity Direction of feed Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
1PIN MARK
1.0MAX
S
(0.22)
( reel on the left hand and you pull out the tape on the right hand
)
0.08
S 2.10.1 1.0
1 20 16 15 11 5 6 10
C0.2
0.40.1
0.5
+0.05 0.25 -0.04
2.10.1
+0.03 0.02 -0.02
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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17/17
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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